I found sample code to use the BSCAN_SPARTAN3 module in Xilinx’s FPGAs. This allows the internal design to be accessed through the JTAG chain through two registers.
Here’s a sample implementation, which uses VHDL and Python
To extract the file, simply copy everything from #!/bin/bash until the end. The script will extract the files. Don’t worry about the checksum errors, they are produced because Google blocks email addresses and there is one in the comments section of the file. When google alters it, it makes the checksum fail. The rest of the file is fine.